1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) fabrication and devices, and more particularly to a method for forming a capacitor of a dynamic random access memory cell and the cell formed thereby.
2. Description of the Prior Art
In order to satisfy demands for high density DRAM semiconductor chips, micro-miniaturization employing sub-micron features are employed. However, to achieve high DRAM densities at low costs, new designs and technology integration are needed. Typically, a DRAM storage cell comprises a transistor and a capacitor wherein the gate of the transistor is controlled by a word line signal, and data represented by the logic level of the storage capacitor is written into or read out of the capacitor through a bit line signal.
One recent design and fabrication process for a DRAM cell is set forth in U.S. Pat. No. 5,792,960, incorporated herein by reference, wherein a polysilicon DRAM capacitor is vertically aligned with a polysilicon transistor gate structure while using an underlying bit line embedded in the device isolation insulator. Still other methods for fabricating DRAM capacitors and DRAM cells can be found with reference to U.S. Pat. Nos. 5,482,886; 5,648,290; 5,677,222; and 5,792,690, all of which are incorporated herein by reference. Present methods for achieving sub-micron features, such as stacked/trench capacitors for EDRAM cells, is believed to be overly complicated
Generally, it is desirable to fabricate a DRAM cell having a high capacitance capacitor in order to maintain a high signal to noise ratio in reading the memory cell and to reduce xe2x80x9csoftxe2x80x9d errors (due to alpha particle interference). However, it is also desirable to achieve small feature size and to utilize a cost effective fabrication process. Since, for any given dielectric, the greater the capacitor area the greater the capacitance, one may compromise capacitance and cell size. However, rather than reduce capacitance, it would be desirable to use films having a higher dielectric constant so that size can be reduced without reducing total capacitance. Also, cost effective fabrication usually requires a minimum number of processing steps and mask registrations for the formation of the DRAM capacitor. Hence, it is desirable to reduce the number of masks used in processing and/or device size in an integrated logic-memory chip where processing for logic and memory are compatible.
A method is provided for forming a DRAM capacitor of a DRAM cell having a MOSFET that requires only one additional mask subsequent to formation of the MOSFET. The MOSFET is conventionally formed in and on a semiconductor substrate and the storage capacitor is formed in a trench provided in a top dielectric of the transistor, rather than in the adjoining silicon thus utilizing less substrate surface area. The method of the invention can reduce the DRAM cell to about 0.5 square microns in a technique that is compatible with forming both the memory and the processing devices on a single integrated substrate.